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Segger J-Link ULTRA JTAG Debugger

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J-Link Ultra is a JTAG/SWD emulator designed for ARM/Cortex and other supported CPUs. It is fully compatible to the standard J-Link and works with the same PC software.

 

 

Based on the highly optimized and proven J-Link, it offers even higher speed as well as target power measurement capabilities due to the faster CPU, built-in FPGA and High speed USB interface

 


It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, Windows Vista or Windows 7. J-Link Ultra has a built-in 20-pin JTAG/SWD connector.

 

 

 

Features:


Fully compatible to the standard J-Link
Very high performance for all supported CPU cores
Hi-Speed-USB 2.0 interface
Serial Wire Debug supported
Serial Wire Viewer (SWV) supported
SWV: UART and Manchester encoding supported
SWO sampling frequencies up to 25 MHz
Target power can be supplied
Target power consumption can be measured with high accuracy.
Direct download into flash memory of most popular microcontrollers supported
Any ARM7/ARM9/ARM11, Cortex-M0/M1/M3 core support, including thumb mode
Automatic core recognition
JTAG speed up to 25 MHz
Seamless integration into the IAR Embedded Workbench IDE
No power supply required, powered through USB
Support for adaptive clocking
All JTAG signals can be monitored, target voltage can be measured
Support for multiple devices
Fully plug and play compatible
Standard 20-pin JTAG connector
Wide target voltage range: 1.8V - 5.0V
USB and 20-pin ribbon cable included
Memory viewer (J-Mem) included
TCP/IP server included, which allows using J-Link via TCP/IP networks
RDI interface available, which allows using J-Link with RDI compliant software
Flash programming software (J-Flash) available
Flash DLL available, which allows using flash functionality in custom applications
Software Developer Kit (SDK) available
Embedded Trace Buffer (ETB) support
Optical isolation adapter available
Target power supply: J-Link can supply up to 300 mA to target with overload protection

 

 

Being fastest in its class, the regular J-Link already sets a very high standard for debugging and download performance.

 

J-Link Ultra raises the bar even higher, aiming to be the fastest emulator available!

 

Since the PC-Software, form factor and connectors are the same as for the regular J-Link, it can be used with any software compatible with J-Link and any adapter, such as the JTAG-isolator.


Just like for the regular J-Link, the Flash Breakpoints option for enhanced debugging of programs running in the flash of microcontrollers is available.

 

The J-Link is natively supported by IAR EWARM, KEIL µVision, Rowley Crossworks, and CodeSourcery G++. With the RDI and GDB-Server extensions, the supported tool-chains also include Atollic TrueStudio, Yagarto, and other RDI or GDB compatible development environments. If your development environment does not supply a Flash Loader for your device, the J-Link Ultra includes flash loaders designed for all popular devices with internal Flash.

 

The Flash Breakpoints option allows the user to set an unlimited number of breakpoints while debugging within a device’s internal flash memory. This overcomes the hardware breakpoint limitations present in most common microcontrollers (2 on ARM7/9, 4 on Cortex-M0, typically 6 on Cortex-M3 and 8 on Renesas RX).

 


Specifications

General

Supported OS

Microsoft Windows 2000
Microsoft Windows XP
Microsoft Windows XP x64
Microsoft Windows 2003
Microsoft Windows 2003 x64
Microsoft Windows Vista
Microsoft Windows Vista x64
Windows 7
Windows 7 x64

Electromagnetic compatibility (EMC)

EN 55022, EN 55024

Operating temperature

+5°C ... +60°C

Storage temperature

-20°C ... +65 °C

Relative humidity (non-condensing)

Max. 90% rH

Mechanical

Size (without cables)

100mm x 53mm x 27mm

Weight (without cables)

73g

Available Interfaces

USB interface

USB 2.0, Hi-Speed

Target interface

JTAG/SWD 20-pin

External (SPI) analog power measurement interface

4-pin (Pins 14, 16, 18 and 20 of the 20-pin JTAG/SWD interface)

JTAG/SWD Interface, Electrical

Target interface voltage (VIF)

1.8V ... 5V

Target supply voltage

4.5V ... 5V

Target supply current

Max. 300mA

Reset type

Open drain. Can be pulled low or tristated

Reset low level output voltage

VOL <= 10% of VIF

For the whole target voltage range (1.8V <= VIF <= 5V)

LOW level input voltage (VIL)

VIL <= 40% of VIF

HIGH level input voltage (VIH)

VIH >= 60% of VIF

For 1.8V >= VIF <= 3.6V

LOW level output voltage (VOL) with a load of 10 kOhm

VOL <= 10% of VIF

HIGH level output voltage (VOH) with a load of 10 kOhm

VOH >= 90% of VIF

For 3.6 <= VIF <= 5V

LOW level output voltage (VOL) with a load of 10 kOhm

VOL <= 20% of VIF

HIGH level output voltage (VOH) with a load of 10 kOhm

VOH >= 80% of VIF

JTAG/SWD Interface, Timing

SWO sampling frequency

Max. 25 MHz

Data input rise time (Trdi)

Trdi <= 20ns

Data input fall time (Tfdi)

Tfdi <= 20ns

Data output rise time (Trdo)

Trdo <= 10ns

Data output fall time (Tfdo)

Tfdo <= 10ns

Clock rise time (Trc)

Trc <= 10ns

Clock fall time (Tfc)

Trc <= 10ns

Analog power measurement interface

Sampling frequency

50 kHz

Resolution

1 mA

External (SPI) analog interface

SPI frequency

Max. 4 MHz

Samples / sec

Max. 50000

Resolution

Max. 16-bit

 

JMEM Memory Viewer

J-Mem is a small (app. 50 kb) stand-alone application for Microsoft Windows 2000 and Windows XP. It requires a J-Link connected to the USB port and an ARM system connected to J-Link via the JTAG interface.


J-Mem displays memory contents of ARM-systems and allows modifications of RAM and sfrs (Special function registers) while target is running. It makes it possible to look into the memory of an ARM chip at run time; RAM can be modified and sfrs can be written. The type of acces for both read and write access can be selected to be 8/16/32 bit.


It works nicely when modifying sfrs, especially because it writes the sfr only after the complete value has been entered.

jmem

 


J-TAG Performance comparison

The following table lists performance values of popular JTAG emulators for download into RAM:

Product

Download speed

Abatron BDI2000

up to 340 Kbytes/s

Abatron BDI1000

up to 170 Kbytes/s

Amontec JTAGkey

up to 135 Kbytes/s

ARM RealView Multi-ICE

up to 130 Kbytes/s

Hitex Tantino

up to 130 Kbytes/s

Hitex Tanto

up to 400 Kbytes/s

Ronetix PEEDI

up to 409 Kbytes/s

Rowley CrossConnect for ARM

up to 200 Kbytes/s

Segger J-Link

up to 720 Kbytes/s

 

All download speeds are taken from specifications found on manufacturer's website on March 20, 2007. If different values have been found, the highest one has been used. Please note that the actual speed depends on various factors, such as JTAG, clock speed, host CPU core etc.

 

 

Measuring J-Link download speed

 

JLink.exe has been used to measure performance. The hardware consisted of:

  •  PC with 2.6 GHz Pentium 4, running Win2K

  •  USB 2.0 port

  •  USB 2.0 hub

  •  J-Link

  •  Target with ARM7 running at 50 MHz

 

 

 

Multiple devices in the scan chain

J-Link ARM can handle multiple devices in the scan chain. This applies to hardware where multiple chips are connected to the same JTAG connector. As can be seen in the drawing below, the TCK and TMS lines of all JTAG device are connected, while the TDI and TDO lines form a bus.

 

Currently, up to 8 devices in the scan chain are supported. One or more of these devices can be ARM cores; the other devices can be of any other type but need to comply with the JTAG standard.

 

 

multi device

 

 

Multi core debugging

 

J-Link is able to debug multiple cores on one target system connected to the same scan chain.

 

How multi-core debugging works

Multi-core debugging requires multiple debuggers or multiple instances of the same debugger. Two or more debuggers can use the same J-Link / J-Trace simultaneously. Configuring a debugger to work with a core in a multi-core environment does not require special settings. All that is required is proper setup of the scan chain for each debugger. This enables J-Link / J-Trace to debug more than one core on a target at the same time. Both debuggers share the same physical connection.

 

Multi core debugging